STE10A Datasheet, PDF (44/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Registers and descriptors description
STE10/100A
Table 8.
Bit #
4
3
2
1
0
Control/status register description (continued)
Name
Description
--- Reserved
Transmit jabber timer time-out.
1: when the transmit jabber timer expires. The
TJT _{transmit processor will enter the stop state and}
TO (bit 14 of TDES0, transmit jabber time-out
flag) will be asserted.
TDU
Transmit descriptor unavailable.
1: when the next transmit descriptor can not be
obtained by the STE10/100A. The transmission
process is suspended in this situation. To restart
the transmission process, the ownership bit of
the next transmit descriptor should be set to
STE10/100A and, if the transmit automatic
polling is not enabled, a transmit poll demand
command should then be issued.
Transmit process stopped.
TPS
1: while transmit state = stop
Transmit completed interrupt.
TCI ^{1: set when a frame transmission completes with}
IC (bit 31 of TDES1) asserted in the first transmit
descriptor of the frame.
LH = High Latching and cleared by writing 1.
CSR6 (offset = 30h), NAR - Network access register
31~22
21
20
--- Reserved
Store and forward for transmit
SF 0: disable
1: enable, ignore the transmit threshold setting
--- Reserved
19
18~16
15~14
13
SQE
-----
TR
ST
SQE disable
0: enable SQE function for 10BASE-T operation.
The STE10/100A provides SQE test function for
10BASE-T half duplex operation.
1: disable SQE function.
Reserved
Transmit threshold control
00: 128-bytes (100Mbps), 72-bytes (10Mbps)
01: 256-bytes (100Mbps), 96-bytes (10Mbps)
10: 512-bytes (100Mbps), 128-bytes (10Mbps)
11: 1024-bytes (100Mbps), 160-bytes (10Mbps)
Stop transmit
0: stop (default)
1: start
Default
0
0
0
0
0
1
00
0
RW type
RO/LH*
RO/LH*
RO/LH*
RO/LH*
R/W*
R/W*
R/W*
R/W
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