STE10A Datasheet, PDF (32/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Registers and descriptors description
STE10/100A
4.1.1
STE10/100A configuration registers description
Table 6.
Bit #
Configuration registers description
Name
Description
Default RW type
CR0 (offset = 00h), LID - Loaded identification number of device and vendor
31~16
15~0
LDID
Loaded device ID, the device ID number loaded from From
serial EEPROM
EEPROM
R/O
LVID
Loaded vendor ID, the vendor ID number loaded
from serial EEPROM
From
R/O
EEPROM
From EEPROM: Loaded from EEPROM
CR1 (offset = 04h), CSC - Configuration command and status
Status parity error.
31
SPE ^{1: means that STE10/100A detected a parity error.}
0
R/W
This bit will be set even if the parity error response
(bit 6 of CR1) is disabled.
Status system error.
30
SES 1: means that STE10/100A asserted the system
error pin.
0
R/W
Status master abort.
29
SMA 1: means that STE10/100A received a master abort
0
R/W
and has terminated a master transaction.
Status target abort.
28
STA _{1: means that STE10/100A received a target abort}
0
R/W
and has terminated a master transaction.
27
--- Reserved
Status device select timing. Indicates the timing of
26, 25 SDST ^{the chip’s assertion of device select.}
01
R/O
01: indicates a medium assertion of DEVSEL#.
Status data parity report.
1: when three conditions are met:
a. STE10/100A asserted parity error (PERR#) or it
24
SDPR detected parity error asserted by another device.
0
R/W
b. STE10/100A is operating as a bus master.
c. STE10/100A’s parity error response bit (bit 6 of
CR1) is enabled.
Status fast back-to-back.
23
SFBB Always 1, since STE10/100A has the ability to
accept fast back to back transactions.
1
R/O
22~21
--- Reserved
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