STE10A Datasheet, PDF (40/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Registers and descriptors description
STE10/100A
Table 8.
Bit #
Control/status register description
Name
Description
CSR0 (offset = 00h), PAR - PCI access register
31~25
24
23
22
21
20~19
18,17
16
15, 14
13 ~ 8
---
MWIE
MRLE
---
MRME
---
TAP
---
CAL
PBL
Reserved
Memory write and invalidate enable.
1: enable STE10/100A to generate memory
write invalidate command. The STE10/100A will
generate this command while writing full cache
lines.
0: disable generating memory write invalidate
command. The STE10/100A will use memory
write commands instead.
Memory read line enable.
1: enable STE10/100A to generate memory read
line command when read access instruction
reaches the cache line boundary. If the read
access instruction doesn’t reach the cache line
boundary then the STE10/100A uses the
memory read command instead.
Reserved
Memory read multiple enable.
1: enable STE10/100A to generate memory read
multiple commands when reading a full cache
line. If the memory is not cache-aligned, the
STE10/100A uses the memory read command
instead.
Reserved
Transmit auto-polling in transmit suspended
state.
00: disable auto-polling (default)
01: polling own-bit every 200 us
10: polling own-bit every 800 us
11: polling own-bit every 1600 us
Reserved
Cache alignment. Address boundary for data
burst, set after reset
00: reserved (default)
01: 8 DW boundary alignment
10: 16 DW boundary alignment
11: 32 DW boundary alignment
Programmable burst length. This value defines
the maximum number of DW to be transferred in
one DMA transaction.
Value: 0 (unlimited), 1, 2, 4, 8, 16 (default), 32
Default
0
0
0
00
00
000000
RW type
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
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