STE10A Datasheet, PDF (62/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Registers and descriptors description
STE10/100A
Table 10. Transceiver registers description (continued)
Bit #
Name
Description
Link partner’s 100BASE-T4 ability.
9
LPT4 0: link partner without 100BASE-T4 ability.
1: link partner with 100BASE-T4 ability.
Link partner’s 100BASE-TX full duplex ability.
0: link partner without 100BASE-TX full duplex
8
LPTXF ability.
1: link partner with 100BASE-TX full duplex
ability.
Link partner’s 100BASE-TX half duplex ability.
7
LPTXH 0: link partner without 100BASE-TX.
1: link partner with 100BASE-TX ability.
Link partner’s 10BASE-T full duplex ability.
6
LP10F
0: link partner without 10BASE-T full duplex
ability.
1: link partner with 10BASE-T full duplex ability.
Link partner’s 10BASE-T half duplex ability.
5
LP10H 0: link partner without 10BASE-T ability.
1: link partner with 10BASE-T ability.
4~0
LPSF
Link partner select field. Standard IEEE 802.3 =
00001
Default
0
0
0
0
0
0
RW type
RO
RO
RO
RO
RO
RO
XR6(offset = cch) - ANE, auto-negotiation expansion
15~5
--- reserved
0
Parallel detection fault.
4
PDF 0: no fault detected.
0
1: a fault detected via parallel detection function.
Link partner’s next page ability.
3
LPNP 0: link partner without next page ability.
0
1: link partner with next page ability.
STE10/100A’s next page ability.
2
NP _{Always 0; STE10/100A does not support next}
0
page ability.
Page received.
1
PR 0: no new page has been received.
0
1: a new page has been received.
Link partner auto-negotiation ability.
0
LPAN 0: link partner has no auto-negotiation ability.
0
1: link partner has auto-negotiation ability.
LH = High Latching and cleared by reading.
RO
RO/LH*
RO
RO
RO/LH*
RO
62/82