STE10A Datasheet, PDF (66/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Registers and descriptors description
STE10/100A
4.4
4.4.1
Note:
Descriptors and buffer management
The STE10/100A provides receive and transmit descriptors for packet buffering and
management.
Receive descriptor
Table 11. Receive descriptor table
31
RDES0 Own
Status
RDES1
---
Control
Buffer2 byte-count
RDSE2
Buffer1 address (DW boundary)
RDSE3
Buffer2 address (DW boundary)
0
Buffer1 byte-count
Descriptors and receive buffers addresses must be long-word aligned
Table 12. Receive descriptor description
Bit#
Name
Description
RDES0
31
30-16
15
14
13-12
11
10
OWN
FL
ES
DE
DT
RF
MF
Own bit
1: indicates that newly received data can be put into this descriptor
0: Host has not yet processed the received data currently in this descriptor.
Frame length, including CRC. This field is valid only in a frame’s last
descriptor.
Error summary. Logical OR of the following bits:
0: overflow
1: CRC error
6: late collision
7: frame too long
11: runt packet
14: descriptor error
This field is valid only in a frame’s last descriptor.
Descriptor error. This bit is valid only in a frame’s last descriptor.
1: the current valid descriptor is unable to contain the packet being currently
received. The packet is truncated.
Data type
00: normal
01: MAC loop-back
10: Transceiver loop-back
11: remote loop-back
These bits are valid only in a frame’s last descriptor.
Runt frame (packet length < 64 bytes). This bit is valid only in a frame’s last
descriptor.
Multicast frame. This bit is valid only in a frame’s last descriptor.
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