STE10A Datasheet, PDF (52/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Registers and descriptors description
STE10/100A
Table 8.
Bit #
22~ 20
19~17
16
15
14~0
Control/status register description (continued)
Name
Description
Transmit state. Reports the current transmission
state only, no interrupt will be generated.
000: stop
001: read descriptor
010: transmitting
TS
011: FIFO fill, read the data from memory and
put into FIFO
100: reserved
101: reserved
110: suspended, unavailable transmit descriptor
or FIFO overflow
111: write descriptor
Receive state. Reports current receive state
only, no interrupt will be generated.
000: stop
001: read descriptor
010: check this packet and pre-fetch next
descriptor
RS _{011: wait for receiving data}
100: suspended
101: write descriptor
110: flush the current FIFO
111: FIFO drain, move data from receiving FIFO
into memory
ANISS
Added normal interrupt status summary.
1: whenever any of the added normal interrupts
occur.
AAISS
Added abnormal interrupt status summary.
1: whenever any of the added abnormal
interrupts occur.
These bits are the same as the status register of
CSR5, and are accessible through either CSR5
or CSR16.
Default
000
000
0
1
LH* = High Latching and cleared by writing 1
CSR17 (offset = 84h), ACSR7- Assistant CSR7 (Interrupt enable register 2)
31
TEIE Transmit early interrupt enable
0
30
REIE Receive early interrupt enable
0
29
XIE Transceiver (XCVR) interrupt enable
0
28
TDIE Transmit deferred interrupt enable
0
27
--- Reserved
26
PFRIE PAUSE frame received interrupt enable
0
25~17
--- Reserved
RW type
RO
RO
RO/LH*
RO/LH*
R/W
R/W
R/W
R/W
R/W
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