STE10A Datasheet, PDF (61/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STE10/100A
Registers and descriptors description
Table 10. Transceiver registers description (continued)
Bit #
Name
Description
XR4(offset = c4h) - ANA, Auto-negotiation advertisement
Next page ability.
15
NXTPG Always 0; STE10/100A does not provide next
page ability.
14
--- reserved
13
12,11
Remote fault function.
RF
1: remote fault function present
--- Reserved
Flow control function ability.
10
FC _{1: supports PAUSE operation of flow control for}
full duplex link.
100BASE-T4 ability.
9
T4 Always 0; STE10/100A does not provide
100BASE-T4 ability.
100BASE-TX full duplex ability.
8
TXF
1: 100Base-TX full duplex ability supported
100BASE-TX half duplex ability.
7
TXH
1: 100Base-TX ability supported.
10BASE-T full duplex ability.
6
10F
1: 10Base-T full duplex ability supported.
10BASE-T half duplex ability.
5
10H
1: 10Base-T ability supported.
4~0
SF Select field. Default 00001=IEEE 802.3
XR5(offset = c8h) - ANLP, Auto-negotiation link partner ability
15
14
13
12,11
10
LPNP
LPACK
LPRF
---
LPFC
Link partner next page ability.
0: link partner without next page ability.
1: link partner with next page ability.
Received link partner acknowledge.
0: link code word not yet received.
1: link partner successfully received
STE10/100A’s link code word.
Link partner’s remote fault status.
0: no remote fault detected.
1: remote fault detected.
Reserved
Link partner’s flow control ability.
0: link partner without PAUSE function ability.
1, link partner with PAUSE function ability for full
duplex link.
Default
0
0
1
0
1
1
1
1
00001
0
0
0
0
0
RW type
RO
R/W
R/W
RO
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
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