STE10A Datasheet, PDF (68/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Registers and descriptors description
STE10/100A
4.4.2
Transmit descriptor
Table 13. Receive descriptor table
31
TDES0 Own
TDES1
---
Control
TDSE2
TDSE3
Status
Buffer2 byte-count
Buffer1 address
Buffer2 address
Table 14. Transmit descriptor description
Bit#
Name
Description
TDSE0
31
30-24
23-22
21-16
15
14
13-12
11
10
9
8
7
6-3
2
1
0
TDES1
31
30
OWN
---
UR
---
ES
TO
-----
LO
NC
LC
EC
HF
CC
-----
UF
DE
Own bit
1: Indicates this descriptor is ready to transmit
0: No transmit data in this descriptor.
Reserved
Under-run count
Reserved
Error summary. Logical OR of the following bits:
1: under-run error
8: excessive collision
9: late collision
10: no carrier
11: loss carrier
14: jabber time-out
Transmit jabber time-out
Reserved
Loss of carrier
No carrier
Late collision
Excessive collision
Heartbeat fail
Collision count
Reserved
Under-run error
Deferred
IC Interrupt completed
LS Last descriptor
0
Buffer1 byte-count
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