STE10A Datasheet, PDF (59/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STE10/100A
Registers and descriptors description
Table 10. Transceiver registers description
Bit #
Name
Description
Default RW type
XR0(offset = b4h) - XCR, XCVR control register. The default value is chosen as listed below.
Transceiver reset control.
15
XRST ^{1: reset transceiver. This bit will be cleared by}
0
R/W
STE10/100A after transceiver reset has
completed.
Transceiver loop-back mode select.
14
XLBEN 1: transceiver loop-back mode is selected. OM
0
R/W
(CSR6 bits 11,10) of must contain 00.
Network speed select. This bit will be ignored if
Auto-negotiation is enabled (ANEN, XR0 bit 12).
13
SPSEL _{1:100Mbps is selected.}
1
R/W
0:10Mbps is selected.
Auto-negotiation ability control.
12
ANEN 1: Auto-negotiation function is enabled.
0: Auto-negotiation is disabled.
1
R/W
Power down mode control.
11
PDEN ^{1: transceiver power-down mode is selected. In}
0
R/W
this mode, the STE10/100A transceivers are
turned off.
10
--- reserved
0
RO
Re-start auto-negotiation process control.
9
RSAN ^{1: Auto-negotiation process will be restarted.}
0
R/W
This bit will be cleared by STE10/100A after the
Auto-negotiation has restarted.
Full/half duplex mode select.
8
DPSEL ^{1: full duplex mode is selected. This bit will be}
0
R/W
ignored if auto-negotiation is enabled (ANEN,
XR0 bit 12).
Collision test control.
7
COLEN
1: collision test is enabled.
0
R/W
6~0
--- Reserved
0
RO
R/W = Read/Write able. RO = Read only.
XR1(offset = b8h) - XSR, XCVR status register. All the bits of this register are read only.
100BASE-T4 ability.
15
T4
0
RO
Always 0, since STE10/100A has no T4 ability.
100BASE-TX full duplex ability.
14
TXFD Always 1, since STE10/100A has 100BASE-TX
1
RO
full duplex ability.
100BASE-TX half duplex ability.
13
TXHD _{Always 1, since STE10/100A has 100BASE-TX}
1
RO
half duplex ability.
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