STE10A Datasheet, PDF (74/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Electrical specifications and timings
Figure 16. PCI clock waveform
0.475Vcc
0.4Vcc
0.6Vcc
0.2Vcc
Th
0.325Vcc
Tl
Tc
STE10/100A
0.4Vcc, p-to-p
minimum
Table 21. X1 specifications
Symbol
Parameter
TX1d X1 duty cycle
TX1p X1 period
TX1t X1 tolerance
TX1C_L X1 load capacitance
Table 22. PCI timing
Symbol
Parameter
Clock to signal valid delay
Tval
(bussed signals)
Clock to signal valid delay
Tval(ptp)
(point to point)
Ton Float to active delay
Toff Active to float delay
Input set up time to clock
Tsu
(bussed signals)
Input set up time to clock
Tsu(ptp)
(point to point)
Th Input hold time from clock
Th Input hold time from clock
Trst
Reset active time after power
stable
Trst-clk
Reset active time after clk
stable
Trst-off
Reset active to output float
delay
Test condition
Test condition
Min.
45
Typ. Max. Units
50 55 %
30
ns
+/-
50
PPM
18 pF
Min.
2
Typ. Max. Units
11 ns
2
11 ns
2
ns
28 ns
7
ns
10,12
0
0
1
100
ns
ns
ns
ms
µs
40 ns
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