STE10A Datasheet, PDF (28/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Functional description
STE10/100A
3.8
Wake on LAN function
The STE10/100A can assert a signal to wake up the system when it has received a Magic
Packet from the network. The wake on LAN operation is described as follow.
The Magic Packet format
– Valid destination address that can pass the address filter of the STE10/100A
– Payload of the frame including at least 6 contiguous ‘FF’ followed immediately by
16 repetitions of IEEE address
– The frame can contain multiple ‘six FF + sixteen IEEE address’ pattern
– Valid CRC
The wake on LAN operation
The wake on LAN enable function is controlled by WOL (bit 18 of CSR18), which is loaded
from EEPROM after reset or programmed by driver software. If WOL is set and the
STE10/100A receives a Magic Packet, it will assert the PME# signal (active low) to indicate
reception of a wake up frame and will set the PME status bit (bit 15 of CSR20).
3.9
3.9.1
ACPI power management function
The STE10/100A has a built-in capability for power management (PM) which is controlled by
the host system.
The STE10/100A will provide:
– Compatibility with device class power management reference specification
– Network device class, draft proposal v0.9, october 1996
– Compatibility with ACPI, Rev 1.0, december 22, 1996
– Compatibility with PCI bus power management interface specification, Rev 1.0,
january 6, 1997
– Compatibility with AMD Magic Packet™ Technology.
Power states
DO (Fully on)
In this state the STE10/100A operates with full functionality and consumes normal power.
While in the D0 state, if the PCI clock is lower than 16MHz, the STE10/100A may not
receive or transmit frames properly.
D1, D2, and D3_hot
In these states, the STE10/100A doesn’t respond to any accesses except configuration
space and full function context in place. The only network operation the STE10/100A can
initiate is a wake-up event.
D3_cold (Power removed)
In this state all function context is lost. When power is restored, a PCI reset must be
asserted and the function will return to D0.
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