STE10A Datasheet, PDF (34/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Registers and descriptors description
STE10/100A
Table 6.
Bit #
Configuration registers description (continued)
Name
Description
Default RW type
CR3 (offset = 0ch), LT - Latency timer
31~16
--- Reserved
Latency timer. This value specifies the latency timer
of the STE10/100A in units of PCI bus clock cycles.
Once the STE10/100A asserts FRAME#, the latency
15~ 8
LT timer starts to count. If the latency timer expires and 40h
R/W
the STE10/100A is still asserting FRAME#, the
STE10/100A will terminate the data transaction as
soon as its GNT# is removed.
Cache line size. This value specifies the system
cache line size in units of 32-bit double words (DW).
The STE10/100A supports cache line sizes of 8, 16,
or 32 DW. CLS is used by the STE10/100A driver to
7~0
CLS program the cache alignment bits (bit 14 and 15 of
08h
R/W
CSR0) which are used for cache oriented PCI
commands, for example, memory-read-line,
memory-read-multiple, and memory-write-and-
invalidate.
CR4 (offset = 10h), IOBA - I/O base address
31~ 7
IOBA
I/O base address. This value indicate the base
address of PCI control and status register
(CSR0~28), and transceiver registers (XR0~10).
0
R/W
6~1
--- Reserved
I/O space indicator.
0
IOSI 1: means that the configuration registers map into
1
RO
I/O space.
CR5 (offset = 14h), MBA - Memory base address
Memory base address. This value indicate the base
31~ 7
MBA
address of PCI control and status
register(CSR0~28), and transceiver
0
R/W
registers(XR0~10).
6~1
--- Reserved
Memory space indicator.
0
IOSI 1: means that the configuration registers map into
0
RO
I/O space.
CR11 (offset = 2ch), SID - Subsystem ID
31~16
SID
Subsystem ID. This value is loaded from EEPROM
From
as a result of power-on or hardware reset.
EEPROM
RO
15~ 0
SVID
Subsystem vendor ID. This value is loaded from
EEPROM as a result power-on or hardware reset.
From
EEPROM
RO
CR12 (offset = 30h), BRBA - Boot ROM base address. This register should be initialized before
accessing the boot ROM space.
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