STE10A Datasheet, PDF (64/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Registers and descriptors description
STE10/100A
Table 10.
Bit #
0
Transceiver registers description (continued)
Name
Description
REF
Receive error full interrupt.
0: the receive error number is less than 64.
1: 64 error packets is received.
LH = High Latching and cleared by reading.
XR9(offset = d8h) - XIE, XCVR interrupt enable register
15~7
6
5
4
---
ANCE
RFE
LDE
Reserved
Auto-negotiation completed interrupt enable.
0: disable auto-negotiation completed interrupt.
1: enable auto-negotiation complete interrupt.
Remote fault detected interrupt enable.
0: disable remote fault detection interrupt.
1: enable remote fault detection interrupt.
Link down interrupt enable.
0: disable link fail interrupt.
1: enable link fail interrupt.
Auto-negotiation acknowledge interrupt enable.
3
ANAE 0: disable link partner acknowledge interrupt
1: enable link partner acknowledge interrupt.
Parallel detection fault interrupt enable.
2
PDFE 0: disable fault parallel detection interrupt.
1: enable fault parallel detection interrupt.
Auto-negotiation page received interrupt enable.
0: disable auto-negotiation page received
1
ANPE interrupt.
1: enable auto-negotiation page received
interrupt.
RX_ERR full interrupt enable.
0
REFE 0: disable rx_err full interrupt.
1: enable rx_err interrupt.
XR10(offset = dch) - 100CTR, 100BASE-TX control register
15,14
--- Reserved
Disable the RX_ERR counter.
0: the receive error counter - RX_ERR is
13
DISRER enabled.
1: the receive error counter - RX_ERR is
disabled.
Auto-negotiation completed. This bit is the same
as bit 5 of XR1.
12
ANC 0: the auto-negotiation process has not
completed yet.
1: the auto-negotiation process has completed.
Default
0
0
0
0
0
0
0
0
0
0
RW type
RO/LH*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
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