STE10A Datasheet, PDF (77/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STE10/100A
Figure 20. Serial EEPROM timings
CS
Tecss
CLK
Tedts Tedth
DI
Electrical specifications and timings
Tecsh
Tecsl
Table 25. 10BASE-T normal link pulse (NLP) timings specifications
Symbol
Parameter
Test condition
Min.
Typ. Max. Units
Tnpw NLP width
10Mbps
100
ns
Tnpc NLP period
10Mbps
8
24 ms
Figure 21. Normal link pulse timings
Tnpw
Tnpc
Table 26. Auto-negotiation fast link pulse (FLP) timings specifications
Symbol
Parameter
Test condition
Min.
Typ. Max. Units
Tflpw
Tflcpp
Tflcpd
-
Tflbw
Tflbp
FLP Width
Clock pulse to clock pulse
period
Clock pulse to data pulse
period
Number of pulses in one
burst
Burst width
FLP burst period
100
ns
111
125 139 µs
55.5
62.5 69.5 µs
17
33
#
2
ms
8
16 24 ms
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