STE10A Datasheet, PDF (65/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STE10/100A
Registers and descriptors description
Table 10. Transceiver registers description (continued)
Bit #
Name
Description
11, 10
9
8
7
6
5
4~2
1
0
--- Reserved
Enable remote loop-back function.
ENRLB _{1: enable remote loop-back (CSR6 bits 11 and}
10 must be 00).
ENDCR
Enable DC restoration.
0: disable DC restoration.
1: enable DC restoration.
ENRZI
Enable the conversions between NRZ and NRZI.
0: disable the data conversion between NRZ and
NRZI.
1: enable the data conversion of NRZI to NRZ in
receiving and NRZ to NRZI in transmitting.
--- Reserved
ISOTX
Transmit Isolation. When 1, isolate from MII and
tx+/-. This bit must be 0 for normal operation
CMODE
Reports current transceiver operating mode.
000: in auto-negotiation
001: 10Base-T half duplex
010: 100Base-TX half duplex
011: reserved
100: reserved
101: 10Base-T full duplex
110: 100Base-TX full duplex
111: isolation, auto-negotiation disable
DISMLT
Disable MLT3.
0: the MLT3 encoder and decoder are enabled.
1: the MLT3 encoder and decoder are bypassed.
Disable scramble.
DISCRM 0: the scrambler and de-scrambler is enabled.
1: the scrambler and de-scrambler are disabled.
Default
1
0
1
1
0
000
0
0
RW type
R/W
R/W
R/W
R/W
RO
R/W
R/W
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