STE10A Datasheet, PDF (48/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Registers and descriptors description
STE10/100A
Table 8. Control/status register description (continued)
Bit #
Name
Description
Serial EEPROM clock.
1
SCLK High/Low this bit to provide the clock signal for
EEPROM.
Serial EEPROM chip select.
0
SCS
1: selects the serial EEPROM chip.
CSR11 (offset = 58h), TMR - General - Purpose timer
31~17
16
15~0
---
COM
GTV
Reserved
Continuous operation mode.
1: sets the general-purpose timer in continuous
operating mode.
General-purpose timer value.
Sets the counter value. This is a count-down
counter with a cycle time of 204us.
CSR13 (offset = 68h), WCSR – Wake-up control/status register
31
30
29
28
27
26
25
24-18
17
16
15-11
10
--- Reserved
CRCT
CRC-16 type
0: Initial contents = 0000h
1: Initial contents = FFFFh
WP1E Wake-up pattern one matched enable
WP2E Wake-up pattern two matched enable
WP3E Wake-up pattern three matched enable
WP4E Wake-up pattern four matched enable
WP5E Wake-up pattern five matched enable
--- Reserved
Link off detect enable. The STE10/100A will set
LinkOFF the LSC bit of CSR13 after it has detected that
link status has switched from ON to OFF.
Link on detect enable. The STE10/100A will set
LinkON the LSC bit of CSR13 after it has detected that
link status has switched from OFF to ON.
--- Reserved
WFRE
Wake-up frame received enable. The
STE10/100A will include the “Wake-up Frame
Received” event in its set of wake-up events. If
this bit is set, STE10/100A will assert PMEST bit
of PMR1 (CR49) after STE10/100A has received
a matched wake-up frame.
Default
1
1
0
0
0
0
0
0
0
0
0
0
0
RW type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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