STE10A Datasheet, PDF (67/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STE10/100A
Registers and descriptors description
Table 12. Receive descriptor description (continued)
Bit#
Name
Description
9
FS First descriptor
8
LS Last descriptor
7
TL
Packet too long (packet length > 1518 bytes). This bit is valid only in a
frame’s last descriptor.
6
CS
Late collision. Set when collision is active after 64 bytes. This bit is valid only
in a frame’s last descriptor
Frame type. This bit is valid only in a frame’s last descriptor.
5
FT 0: 802.3 type
1: Ethernet type
4
RW
Receive watchdog (refer to CSR15, bit 4). This bit is valid only in a frame’s
last descriptor.
3
reserved Default = 0
Dribble bit. This bit is valid only in a frame’s last descriptor
2
DB
1: Packet length is not integer multiple of 8-bit
1
CE 1: CRC error. This bit is valid only in a frame’s last descriptor
0
OF 1: Overflow. This bit is valid only in a frame’s last descriptor
RDES1
31~26
25
24
23~22
21~11
10~ 0
---
RER
RCH
---
RBS2
RBS1
Reserved
Receive end of ring. Indicates this descriptor is last, return to base address
of descriptor
Second address chain
Used for chain structure, indicating the buffer 2 address is the next descriptor
address. Ring mode takes precedence over chained mode
Reserved
Buffer 2 size (DW boundary)
Buffer 1 size (DW boundary)
RDES2
31~0
RBA1
Receive buffer address 1. This buffer address should be double word
aligned.
RDES3
31~0
RBA2
Receive buffer address 2. This buffer address should be double word
aligned.
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