COM90C66 Datasheet, PDF (75/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

Modified Version of Page 54 for Rev. D COM90C66 Only.
A0-A19
BALE
nMEMR
nPROM **
nTOPL
IOCHRDY
t1
t3
VALID
t2
t2***
t4
t5
t6
t7
t10
t9
t8
Parameter
min typ max units
t1 Address Set Up to BALE Low *
20
t2 Address Hold after BALE Low *
20
t3 Address, Set Up to nMEMR Low
50
t4 nMEMR Low to nPROM Low
0
t5 nMEMR Low to nTOPL Low
0
t6 nMEMR Low to IOCHRDY Low
0
t7 IOCHRDY Low Pulse Width
100
t8 ^{nMEMR High to nTOPL High}
0
t9 nMEMR High to nPROM HIgh
0
t10 nMEMR High to BALE High (Next Address)
30
nS
nS
nS
25 nS
30 nS
20 nS
165 nS
15 ^nS
30 nS
nS
* _{For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched}
Address Mode.
** _{All PROM accesses are 8-bit only, ROM should use nMEMR as nOE signal and PROM}
as nCS.
*** _{For Revision D devices, if BALE is tied high, then Address must be held for 20 nsec}
after nMEMR Low.
FIGURE 19 - READ PROM CYCLE
75