COM90C66 Datasheet, PDF (26/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

BIT
BIT NAME
7 16-Bit Enable
6 Command
Chaining Enable
5 Decode Mode
4, 3 Extended
Timeout 1, 2
Table 8 - Configuration Register
SYMBOL
DESCRIPTION
16EN
This bit, if high, enables 16-bit operation of the device. A low
level on this bit enables only 8-bit operation. This bit defaults
to a logic "0" upon hardware reset.
CCHEN
This bit, if high, enables the Command Chaining operation of
the device. Please refer to the Command Chaining section of
this document for further details. A low level on this bit
ensures software compatibility with previous SMSC ARCNET
devices. This bit defaults to a logic "0" upon hardware reset.
DECODE
In I/O Mapped applications, this bit is used to choose
between an 8K or 16K block of ROM. In this case, a logic "0"
defines 8K, while a logic "1" defines 16K. In Memory Mapped
applications, this bit and the nENROM input are used to
choose whether the nMEMCS16 signal will be generated by
decoding a block of 128K or 2K. In this case, a logic "0"
defines 128K, while a logic "1" defines 2K. For more details
on the use of this bit, refer to the Memory vs. I/O Cycles
section of this document. This bit defaults to a logic "0" upon
hardware reset.
ET1, ET2
These bits allow the network to operate over longer distances
than the default four miles by controlling the Response Time,
the Idle Time, and the Reconfiguration Time. For proper
network operation, all nodes should be configured for the
same timeout values. The bit combinations follow:
RESPONSE IDLE RECONFIGURATION
ET2 ET1 TIME (µs) TIME (µs) TIME (mS)
0 0 1193.6 1312
1680
0 1 596.8
656
1680
1 0 298.4
328
1680
11
74.7
82
840
These bits default to a logic "1" upon hardware reset.
26