COM90C66 Datasheet, PDF (29/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

Address Pointer Low and High Registers
These read/write registers are each 8-bits wide
and are used in I/O Mapped Mode only. These
bits contain undefined data upon software or
hardware reset. The contents of the Address
Pointer Registers are defined as in Tables 9 and
10. The COM90C66 is capable of incrementing
the address automatically, as explained in Table
10. The contents of the Address Pointer
Registers are undefined upon hardware reset.
INTERNAL RAM
The integration of the 2K x 8 RAM in the
COM90C66 provides several advantages to the
user. Firstly, a significant amount of real estate
is saved due to the elimination of the external
RAM, the external latch, and the multiplexed
address/data bus and control functions which
used to be necessary to interface to the RAM.
Secondly, the system designer is no longer
dependent upon the fluctuating cost of external
RAM. This, and the fact that the entire solution
is more integrated (reducing reliability problems,
assembly time and costs, and layout complexity),
adds up to significant cost reductions.
Thirdly, with the eliminated need for RAM
interfacing signals, several other innovative
features now take the place of the freed-up pins
without the need for increased package size and
pinout. Some of the pins have been replaced
with such useful features as the 16-bit data bus,
the Zero Wait-State signal, the diagnostic pins,
and the choice of Memory or I/O Mapped
functionality.
Fourthly, the COM90C66 is very high speed. The
ability of the device to implement zero wait state
cycles is partly due to the fact that the RAM is
internal to the device.
The Configuration Register contains the I/O
Access bit, which determines whether the RAM
will be configured for sequential I/O mapped
accesses or memory mapped accesses.
Additionally, the Decode Mode bit allows the
choice of 8K or 16K block of ROM if set for I/O
mapped access, or the choice of the activation of
the nMEMCS16 signal upon access to 2K or
128K of RAM if set for memory mapped access.
When the device is configured for a 16-bit data
bus, the on-chip RAM is seen by the processor
as 1K x 16 rather than 2K x 8.
SOFTWARE INTERFACE
The microprocessor interfaces to the COM90C66
via software by accessing the various registers.
These actions were discussed in the Internal
Registers section of this document. Additionally,
it is necessary to understand the details of how
the Internal Registers are used in the transmit
and receive sequences and how the internal RAM
buffer is properly set up. The sequence of events
that tie these actions together are discussed as
follows.
Transmit Sequence
During a transmit sequence, the microprocessor
selects a 256 or 512 byte segment of the RAM
buffer and writes into it. The appropriate buffer
size is specified in the DEFINE
CONFIGURATION command. When long
packets are enabled, the COM90C66 interprets
the packet as a long or short packet, depending
on whether the content of the buffer address 2 is
zero or non-zero. The format of the buffer is
shown in Figure 9. Address 0 contains the
Source Identifier (SID), Address 1 contains the
Destination Identifier (DID), and Address 2
contains, for short packets, the value 256-N,
where N represents the message length, or for
long packets, the value 0, indicating that it is
indeed a long packet. In the latter case, Address
3 would contain the value 512-N, where N
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