COM90C66 Datasheet, PDF (62/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

ADDENDUM 1
DATA SHEET ERRATA FOR REVISION B COM90C66
- The Revision B device does not operate properly in 8-bit mode. Therefore, any reference to 8-bit
operation should be disregarded.
- The Revision B device asserts the nn0WS signal on any memory read or memory write cycle, not
just those associated with the COM90C66. Therefore, the n0WS signal should not be connected
and any reference to Zero Wait State operation should be disregarded.
- The Revision B device, when used in Command Chaining Mode, effectively has only one level of
status bits. Therefore, disregard any reference to double buffering of the interrupt status bits.
- In the Revision B device, the Decode Mode bit has no effect on the memory mapped decode.
Therefore, programming bit 5 of the Configuration Register is ineffective. The nENROM signal
must be used alone to control the decode of either 128K or 2K of memory.
- In the Revision B device, when the device is in 16-bit I/O Mapped Mode, byte writes to odd
locations overwrites the adjacent even location, therefore, byte writes to odd locations should not
be done. It is suggested to perform all writes as word writes, or to temporarily place the device
into 8-bit mode (only for this odd byte write) and then switch back to 16-bit mode for subsequent
accesses.
- In the Revision B device, the nTXLED active width is only 314 µsec.
These corrections apply to this data sheet only when used for Revision B of the COM90C66. This
COM90C66 revision is identified on the part by the letter "B" preceding the date code.
Specific entries in table format appear on the following page.
62