COM90C66 Datasheet, PDF (36/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

Hardware or
Software Reset
Internal POR
nMEMR, nMEMW,
nIOR, nIOW
Microsequencer POR
Internal Reset
The 2nd cycle should be
issued after the 12uS.
102.4 uS or
256 bit clocks
12 uS
1
2
3
Cycles
Enabled
1 During this time, the microsequencer is being reset and the transmitter
portion of the device is disabled.
2 During this time, the microsequencer writes D1H to address 00H, and the Node
ID number to 01H. The transmitter portion of the device is enabled.
3 During this time, the nTOPH, nTOPL, nPROM, nIOCS16, and nMEMCS16 signals are a
a logic "1"; the INTR signal is a logic "0"; the data bus is in the high
impedance state; and the IOCHRDY signal is in normal operation.
FIGURE 10 - INTERNAL RESET SEQUENCE
36