COM90C66 Datasheet, PDF (37/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

it as data to addresses OFH and OEH (Address
Pointer High and Low Registers). The
processor then reads/writes from/to address
0CH (for 8-bit) or OCH and ODH (for 16 bit) the
data found/to be placed at that address. If the
Auto Increment bit is turned on, the Address
Pointer will then increment the address until the
entire packet is obtained/sent. The device in 8-
bit mode increments the pointer by one; 16-bit
mode increments the pointer by two.
Although Sequential I/O Mapped Memory
accesses require more steps than Memory
Mapped accesses, I/O Mapped is just as
efficient as Memory Mapped and does not
require the large block of memory in the host
addressing space that Memory Mapped does.
On the other hand, Memory Mapped access is
more flexible and allows the processor to
analyze the data and make decisions without
emptying the entire packet into system memory.
Refer to Figure 11 for an illustration of the
Sequential I/O Mapped Memory access
operation.
The fact that the COM90C66 contains
independent nMEMCS16 and nIOCS16 signals
provides design versatility. The board can be
software configured for memory mapped or I/O
mapped mode, depending on the system
constraints. The following is some basic
information on both Memory and I/O Modes so
that the user can determine which mode is best
suited for the application:
Memory Mapped Mode:
On any address bus, all address lines must at
some point be latched. On the AT Bus, LA17-
LA23 are not latched on the motherboard. These
are faster, unlatched addresses which can tell
the user immediately when the board is being
accessed. These unlatched lines must be
latched externally by the user. The COM90C66
provides the transparent latch necessary for
these unlatched address lines, as well as the
transparent latch necessary for the additional
unlatched addresses on the Micro
Channel® Bus. On the AT Bus, the lower,
latched address lines (SA0-SA19) come out to
the bus a little later than the unlatched lines.
The existence of the faster, unlatched addresses
allows the COM90C66 board to recognize
accesses immediately, thereby activating the
nMEMCS16 signal for any access to a 128
KByte block of memory. The unlatched version
of the nMEMCS16 mode of the COM90C66 will
meet the timing specification of nMEMCS16 for
every machine, but the limitations are that this
mode may complicate co-existence with other 8-
bit boards in the same 128 KByte block, and an
8-bit auto-boot PROM cannot be supported in
this mode. Therefore, the device must be
configured for memory mapped, 16-bit mode
and the nENROM signal must be high.
In order to use a PROM on the board, the
nMEMCS16 signal should be activated for
decoding to a 2 KByte block of memory. In this
case, the nENROM signal will of course be a
logic "0", enabling the PROM. In this mode, co-
existence with other 8-bit boards will be
supported, as well as the use of the 8-bit PROM,
which will be directly controlled by the device.
However, this is at the expense of slower
nMEMCS16 timing.
Refer to Table 11 for the 16-bit memory mapped
decode table as a function of the nENROM pin
and the DECODE MODE bit. Refer to Figure 12
for an illustration of the generation of the
nMEMCS16 signal.
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