COM90C66 Datasheet, PDF (41/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

cycles to it will also cause a negation of the
IOCHRDY signal for two XTAL1 clocks. Note
that by timing the ready circuitry from the
XTAL1 clock, the IOCHRDY signal is timed in
absolute time rather than relative to the bus
clock.
Either the nOWS signal or the IOCHRDY signal
may be used (but not both), depending upon
speed of the bus. In the case where the
COM90C66 spec meets the bus speed and the
user does not need to "speed up" or "slow down"
the bus, neither the nOWS nor the IOCHRDY
signal should be used. In this case, the Wait
State bit of the Configuration Register should be
reset to logic "0" to configure the device for Zero
Wait State, but the nOWS signal should not be
connected to the bus. Figure 2 shows a jumper
between the nOWS signal and the bus to
illustrate that the signal may be left
unconnected. Table 13 shows the IOCHRDY
and nOWS signal behavior for RAM, internal
register PROM, and external register access.
Table 13 - IOCHRDY and nOWS Signal
WAIT
STATE
BIT
0
1
IOCHRDY
logic "1"
Negated for One or
Two XTAL1 Clocks
nOWS
Activated on Access
logic "1"
Behavior
Please refer to the Zero Wait State and
IOCHRDY Timing Diagram for further details on
the specifications of these two signals.
8-Bit vs. 16-Bit Accesses
In 8-Bit Mode, the nMEMCS16 and nIOCS16
signals remain in their inactive high state. All
register and memory accesses transfer data on
the lower half of the data Bus (D0-D7) while the
upper half (D8-D15) remain in the high
impedance state.
In 16-Bit Mode, the nMEMCS16 signal is
activated for RAM accesses in the memory
Mapped Mode, while the nIOCS16 signal is
activated only for accesses to the pointer or to
the data registers. All other registers are only 8-
bit registers and thus do not require the
nIOCS16 signal. In 16-Bit Mode, register and
memory accesses transfer data on the entire
Data Bus (D0-D15), except for accesses to 8-Bit
registers, which transfer data only on the lower
half of the Data Bus (D0-D7) while the upper
half (D8-D15) remains in the high impedance
state.
8-Bit I/O Mapped Mode:
In order to perform an 8-Bit I/O Mapped Cycle,
the 16-Bit Address Pointer Register should be
programmed by writing the High Register first,
and then the Low Register. All pointer bits are
loaded only after the Low Register is written. In
8-Bit I/O Mapped Mode, the A10-A0 register bits
determine the byte address to be accessed
through the lower portion of the Data Register
(address offset OCH). Refer to Table 14 for
signal level requirements in 8-bit I/O Mapped
accesses.
8-Bit Memory Mapped Mode:
In 8-Bit Memory Mapped Mode, the A10-A0
lines of the Address Bus determine the byte
address to be accessed within the 2K block of
RAM. Refer to Table 14 for signal level
requirements in 8-Bit Memory Mapped
accesses.
16-Bit I/O Mapped Mode:
In order to perform a 16-Bit I/O Mapped Cycle,
the 16-Bit Address Pointer Register should be
programmed by writing the High Register first,
and then the Low Register, or writing both the
High and Low Registers simultaneously. All
pointer bits are loaded only after the Low
Register is written. In 16-Bit I/O Mapped Mode,
the A10-A0 register bits determine the word
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