COM90C66 Datasheet, PDF (32/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

of a dual two-level FIFO, commands to be
transmitted and received, as well as the status
bits, are pipelined.
In order for the COM90C66 to be compatible with
previous SMSC ARCNET devices, the device
defaults to the non-chaining mode. In order to
take advantage of the Command Chaining
operation, the Command Chaining Mode must be
enabled via a logic "1" on bit 6 of the
Configuration Register.
The following is a list of Command Chaining
guidelines for the software programmer to follow.
Further detail can be found in the Transmit
Command Chaining and Receive Command
Chaining sections of this document.
• The device is designed such that the
interrupt service routine latency does not
affect performance. The first interrupt
maybe serviced prior to the generation of the
second interrupt.
• Up to two outstanding transmissions and two
outstanding receptions can be pending at
any given time. The commands may be
given in any order.
• Up to two outstanding transmit interrupts
and two outstanding receive interrupts are
stored by the device, along with their
respective status bits.
• The Interrupt Mask bits act on TTA (Rising
Transition on Transmitter Available) for
transmit operations and TRI (Rising
Transition of Receiver Inhibited) for receive
operations. TTA is set upon completion of a
packet reception only. Typically there is no
need to mask the TTA and TRI bits after
clearing the interrupt.
• The traditional TA and RI bits are still
available to reflect the present status of the
device.
In Command Chaining, the Status Register looks
as follows:
TRI
RI
TA
POR
TEST RECON
TMA
TTA
TRI
TMA
TTA
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