COM90C66 Datasheet, PDF (34/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

immediately. Typically, the interrupt service
routine will read the Status Register. At this
point, the RI bit will be found to be a logic "1".
After reading the Status Register, the CLEAR
RECEIVE INTERRUPT command is issued, thus
resetting the TRI bit and clearing the interrupt.
Note that only the CLEAR RECEIVE
INTERRUPT command will clear the TRI bit and
the interrupt. It is not necessary, however, to
clear the bit or the interrupt right away because
the status of the receive operation is double
buffered in order to retain the results of the first
reception for analysis by the processor,
therefore, the information will remain in the
Status Register until the CLEAR RECEIVE
INTERRUPT command is issued. Note that the
interrupt will remain active until the CLEAR
RECEIVE INTERRUPT command is issued, and
the second interrupt will not occur until the first
interrupt is acknowledged.
The second reception will occur as soon as a
second packet is sent to the node, as long as the
second ENABLE RECEIVE TO PAGE nn
command was issued. The operation is as if a
new ENABLE RECEIVE TO PAGE nn command
has just been issued. A second interrupt will not
occur until the first interrupt is acknowledged by
issuing the CLEAR RECEIVE INTERRUPT
command. After the first Receive status bits are
cleared, the Status Register will again be
updated with the results of the second reception
and a second interrupt resulting from the second
reception will occur. A minimum of 200nS
interrupt inactive time interval is guaranteed.
In the COM90C66, the Receive Inhibit (RI) bit of
the Interrupt Mask Register now masks only the
TRI bit of the Status Register, not the RI bit as in
the non-chaining mode. Since the TRI bit is only
set upon reception of a packet (not by RESET),
and since the TRI bit may easily be set by
issuing a CLEAR RECEIVE INTERRUPT
command, there is no need to use the RI bit of
the Interrupt Mask Register to mask interrupts
generated by the TRI bit of the Status Register.
In both the Command Chaining mode and the
non-chaining mode, the DISABLE RECEIVER
command will cancel the oldest reception, unless
the reception has already begun. If both
receptions should be canceled, two DISABLE
RECEIVER commands should be issued.
RESET DETAILS
Internal Reset Logic
The COM90C66 includes special reset circuitry
to guarantee smooth operation during reset.
Special care is taken to assure proper operation
in a variety of systems and modes of operation.
The design ensures that the COM90C66 will not
disturb the microprocessor or the system bus
until the system has reached a certain level of
operation. Furthermore, in order to eliminate
conflicts with other memory elements, the
internal RAM of the COM90C66 is hidden from
the system until a software reset is issued to the
device and until a valid Node ID is placed in the
Node ID Register. When the system software
determines that no conflicts will arise, it then may
enable the internal memory of the COM90C66
via a software reset.
Because most system buses are inherently
noisy, the COM90C66 contains digital filter
circuitry and a Schmitt Trigger on the RESET IN
signal to reject glitches in order to ensure fault-
free operation.
The COM90C66 supports two reset options;
software and hardware reset. An internal reset
signal of pulse width equal to 102.4 µS is
generated from either a hardware of a software
reset. The hardware reset occurs when a high
signal is asserted on the RESET IN input (pin
65). The minimum reset pulse width is 120 nS
(or 2T+20 nS for crystal frequencies other than
20 MHz, where T = 1/f). This pulse width is
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