COM90C66 Datasheet, PDF (69/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

Modified Version of Pages 16 and 41 for Rev. D COM90C66 Only.
nMEMR,nMEMW
BALE
A19
A18
A17
A16
Transparent
A15
Latch
A14
A13
A12
A11
Transparent
Latch
Comparator
5 to 9
Decoder
MS4
MS3
MS2
MS1
MS0
MEMORY SELECT
FIGURE 4 - MEMORY SELECTOR
nENROM
nMEMR
BALE
A19
A18
A17
A16
A15
A14
A13*
Transparent
Latch
Transparent
Latch
Comparator
5 to 7
Decoder
MS4
MS3
MS2
MS1
MS0
* In I/O 16K X 8 Mode, A13 is a Don't Care
PROM DECODE
FIGURE 5 - PROM SELECTOR
WAIT
STATE
BIT
0
1
IOCHRDY
logic "1"
Negated for Two to Three
XTAL1 Clocks
nOWS
Activated on
Access
logic "1"
TABLE 13 - IOCHRDY and nOWS Signal Behavior
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