COM90C66 Datasheet, PDF (1/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

COM90C66
Data Sheet with Erratas for
Rev. B and Rev. D devices
ARCNET^® Controller/Transceiver with
AT^® Interface and On-Chip RAM
FEATURES
• ARCNET LAN Controller/Transceiver/
• Compatible with the SMSC HYC9058/68/ 88
Support Logic/Dual-Port RAM
(COAX and Twisted Pair Drivers)
• Integrates SMSC COM90C65 with 16-Bit
• Token Passing Protocol with Self
Data Bus, Dual-Port RAM, and Enhanced
Reconfiguration Detection
Diagnostics Circuitry
• Variable Data Length Packets
• Includes IBM® PC/AT® Bus Interface
• 16 Bits CRC Check/Generation
Circuitry
• Includes Address Decoding Circuitry for On-
• Supports 8- and 16-Bit Data Buses
Chip RAM, PROM and I/O
• Full 2K x 8 On-Chip Dual-Port Buffer RAM
• Supports up to 255 Nodes
• Zero Wait State Arbitration for Most AT
• Contains Software Accessible Node ID
Buses
Register
• SMSC COM90C26 Software Compatible
• Compatible with Various Topologies (Star,
• Command Chaining Enhances Performance
Tree, Bus, ...)
• Supports Memory Mapped and Sequential
• On-Board Crystal Oscillator and Reset
I/O Mapped Access to the Internal RAM
Circuitry
Buffer
• Low Power CMOS, Single +5V Supply
GENERAL DESCRIPTION
The SMSC COM90C66 is a special purpose device. Maximum integration has been achieved
communications controller for interconnecting by including the 2K x 8 RAM buffer on the chip,
processors and intelligent peripherals using the providing the immediate benefits of a lower
ARCNET Local Area Network. The COM90C66 device pin count and less board components.
is unique in that it integrates the core ARCNET The performance is enhanced in four ways: a
logic found in Standard Microsystems' original 16-bit data bus for operation with the IBM PC/AT;
COM90C26 and COM90C32 with an on-chip 2K a zero wait state arbitration mechanism, due
x 8 RAM, as well as the 16-bit data bus interface partly to the integration of the RAM buffer on-
for the IBM PC/AT. Because of the inclusion of chip; the ability of the device to do consecutive
the RAM buffer in the COM90C66, a complete transmissions and receptions via the Command
ARCNET node can be implemented with only Chaining operation; and improved diagnostics,
one or two additional ICs (8- or 16-bit allowing the user to control the system more
applications, respectively) and a media driver efficiently. For most AT compatibles, the device
circuit. The ARCNET core remains functionally handles zero wait state transfers.
untouched, eliminating validation and
compatibility concerns. The enhancements exist
in the integration and the performance of the
ARCNET is a registered trademark of Datapoint Corporation
IBM, AT, PC/AT and Micro Channel are registered trademarks of
International Business Machines Corporation
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