COM90C66 Datasheet, PDF (12/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

Acknowledgements
An Acknowledgement is used to acknowledge
reception of a packet or as an affirmative
response to FREE BUFFER ENQUIRIES and is
sent by the following sequence:
• An ALERT BURST
• An ACK (ACKnowledgement--ASCII code
86 HEX) character
ALERT
BURST
ACK
Negative Acknowledgements
A Negative Acknowledgement is used as a
negative response to FREE BUFFER
ENQUIRIES and is sent by the following
sequence:
• An ALERT BURST
• A NAK (Negative AcKnowledgement--ASCII
code 15 HEX) character
ALERT
BURST
NAK
SYSTEM DESCRIPTION
The System Block Diagram shown in Figure 2
illustrates a typical implementation of an
ARCNET node using the COM90C66. The only
external components required to complete an
ARCNET node design are one or two bus
transceivers (for 8-bit or 16-bit applications,
respectively) and the LAN Driver, making the
COM90C66 the most highly-integrated ARCNET
solution. The COM90C66 provides for simple
interfacing to both sides of the ARCNET system,
namely the microprocessor and the
transmission media.
MICROPROCESSOR INTERFACE
The left half of Figure 2 illustrates a typical
COM90C66 interface to the PC. The sections
outlined in dotted lines represent the portion
which distinguishes the 16-bit interface, while
the remaining interface exists for both 8-bit and
16-bit applications. The interface consists of a
20-bit address bus, a 16-bit data bus and a
control bus. All accesses to the internal RAM,
the optional PROM and the internal registers are
controlled by the COM90C66.
The microprocessor's address lines are directly
connected to the COM90C66. The address
decoding circuitry of the COM90C66 monitors
the address bus to determine valid accesses to
the device.
Figure 2 shows octal bus transceivers utilized as
the interface between the microprocessor's data
lines and the COM90C66. The transceivers are
only necessary when interfacing to a high
current drive data bus such as the IBM PC data
bus, and may otherwise be omitted. The
COM90C66 provides the nTOPL and nTOPH
signals which control the direction of the
external transceiver(s). The nTOPL signal is
also activated during PROM Read Cycles.
The microprocessor's control bus is directly
connected to the COM90C66 and is used in
access cycle communication between the device
and the microprocessor. All accesses support
zero wait state arbitration in most machines.
The Control Bus has been optimized to support
the intricacies of the IBM AT Bus and the EISA
Bus.
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