COM90C66 Datasheet, PDF (72/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

Modified Version of Page 51 for Rev. D COM90C66 Only.
A0-A19
nSBHE
BALE
nMEMW
D0-D7 or
D0-D15
nTOPL
nMEMCS16
(Unlatched)
nMEMCS16
(Latched)
VALID
t2
t1
t2 ^***
t3
t8
**
t4
t7
VALID DATA
t5
t9
t6
Parameter
min typ max units
t1 Address, nSBHE Set Up to BALE Low *
20
t2 Address, nSBHE Hold after BALE Low *
20
t3 Address, nSBHE Set Up to nMEMW Low
25
t4 Valid Data Set Up to nMEMW High
30
t5 A17-A19 to nMEMCS16 Low (Unlatched) (128K RAM Decode)
0
t6 A11-A19 to nMEMCS16 (Latched) (2K RAM Decode)
0
t7 Data Hold Time from nMEMW High
9
t8 nMEMW High to BALE High (Next Address)
30
t9 Address, nSBHE Invalid to nMEMCS16 High
0
nS
nS
nS
nS
40 nS
25 nS
nS
nS
nS
* For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address
Mode.
** _{200nS minimum inactive time on consecutive memory writes to the COM90C66.}
*** For Revision D devices, if BALE is tied high, then Address, nSBHE must be held for 20 nsec
after nMEMW Low.
FIGURE 16 - WRITE RAM CYCLE
72