COM90C66 Datasheet, PDF (50/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

A0-A19
nSBHE
BALE
nMEMR
D0-D7or
D0-D15
nTOPH,
nTOPL
nMEMCS16
(Unlatched)
nMEMCS16
(Latched)
VALID
t2
t1
t3
t6
t7
t4
t5
t10
VALID DATA
**
t9
t8
t11
Parameter
min typ max units
t1 Address, nSBHE Set Up to BALE Low*
20
t2 Address, nSBHE Hold after BALE Low*
20
t3 Address, nSBHE Set Up to nMEMR Low
25
t4 nMEMR Low to Valid Data
t5 nMEMR Low to nTOPH, nTOPL Low
0
t6 A19-A17 to nMEMCS16 Low (Unlatched) (128K RAM Decode)
0
t7 A19-A11, BALE High to nMEMCS16 Low (Latched) (2K RAM
0
Decode)
t8 nMEMR High to nTOPH, nTOPL High
0
t9 nMEMR High to Data High Impedance
0
t10 nMEMR High to BALE High (Next Address)
30
t11 Address, nSBHE Invalid to nMEMCS16 High (Unlatched)*
0
nS
nS
nS
80 nS
30 nS
40 nS
25 nS
15 nS
20 nS
nS
nS
* For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address
Mode.
** 130nS minimum inactive time on consecutive memory reads from the COM90C66.
FIGURE 15 - READ RAM CYCLE
50