COM90C66 Datasheet, PDF (3/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

For other machines, the IOCHRDY signal may
be briefly negated to give the device the extra
time necessary to support the faster machines.
Aside from the implementation of a 16-bit data
bus interface, the remaining bus interface logic
is identical to that found in the SMSC
COM90C65, which contains all the support logic
circuitry.
The ARCNET Local Area Network is a token
passing network which operates at a 2.5 Mbps
data rate. A token passing protocol provides
predictable response times because each
network event occurs within a known time
interval. Throughput can be reliably predeter-
mined based upon the number of nodes and
their expected traffic.
The COM90C66 establishes the network
configuration and automatically reconfigures the
token passing order as new nodes are added or
deleted from the network.
The COM90C66 performs address recognition,
CRC checking and generation, packet
acknowledgement, and other network
management functions. The C0M90C66
interfaces directly to the IBM PC/AT or
compatibles. The internal 2K x 8 RAM buffer is
used to hold up to four data packets with a
maximum length of 508 bytes each.
PIN CONFIGURATION
AEN
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
INTR
nBSLED
nTXLED
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
12
74
13
73
14
72
15
71
16
70
17
69
18
68
19
67
20
66
21
22
COM90C66
65
64
23
63
24
62
25
61
26
60
27
59
28
58
29
57
30
56
31
55
32
54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
BALE
nSBHE
nOWS
IOCHRDY
nMEMCS16
nIOCS16
GND
nMEMW
nMEMR
nIOW
nIOR
nTOPL
nTOPH
NC
NC
CACLK
CLK
RXIN
nPULSE2
nPULSE1
nPROM
PACKAGE: 84-Pin P₃LCC
Ordering Information: COM90C66 LJP