COM90C66 Datasheet, PDF (67/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

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SECTION/FIGURE/ENTRY
CORRECTION
Description of Pin Functions, Pin 53 In Revision D, The nENROM signal does not
affect the timing of IOCHRDY.
Configuration Register, Bit 2
For Revision D, the second sentence in the
Description should read "A logic '1' on this bit
negates the IOCHRDY signal for at least two
XTAL1 clocks, creating one wait state".
Wait State Details section;
For Revision D, the fourth paragraph under Wait
Table 13 - IOCHRDY and n0WS State Details should convey that the IOCHRDY
Signal Behavior
signal, when used, is always negated for at least
two XTAL1 clocks. There should be no
distinction made between RAM, internal register,
PROM, and external register cycles. All cycles
will negate IOCHRDY for at least two XTAL1
clocks if IOCHRDY is used. The entry in Table
13 which correlates to the IOCHRDY signal
when the Wait State Bit=1 should read "Negated
for Two to Three XTAL1 Clocks".
Figure 14 - Zero Wait State and For Revision D, the timing parameter for t5
IOCHRDY Timing
should be a minimum of 100 nsec, and a
maximum of 165 nsec.
Description of Pin Functions - Pin 74
For Revision D, the BALE signal is no longer
required to latch the unlatched addresses. All
addresses are latched by the leading edge of the
nMEMR and nMEMW signals for Revision D.
BALE must be tied high or left disconnected if
the device is placed in 8-bit mode.
Description of Pin Functions - Pins For Revision D, the leading edge of these
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signals automatically latch addresses. If the
device is in 8-bit mode, the BALE signal should
be tied high or left disconnected, and the
nMEMR and nMEMW signals should be
responsible for latching the unlatched addresses.
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Figures 4, 5 - Memory Selector, For Revision D, Figures 4 and 5 should contain
PROM Selector
a second Transparent Latch, controlled by the
Control Signal. If BALE is tied high or left
disconnected, the address is latched by only the
second latch-stage, which is controlled only by
the nMEMR and nMEMW signals. If BALE is
connected to the bus, the address is latched by
both the first and second stage latches.
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