COM90C66 Datasheet, PDF (68/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

PAGE
SECTION/FIGURE/ENTRY
CORRECTION
49, 50, 53
Figures 15,16,19 - Read RAM Cycle,
Write RAM Cycle, Read PROM Cycle
For Revision D, a new timing parameter should
exist: Address, SBHE hold after Control
Low...20 nsec minimum. This parameter is only
required if the BALE signal is tied high or left
disconnected.
68