COM90C66 Datasheet, PDF(28/76 Page) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

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COM90C66 Datasheet, PDF (28/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

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Configuration Register

The Configuration Register is a read/write

microprocessor to configure the different modes

of the COM90C66. The register contents are as

in Table 8. The Configuration Register defaults

to the value 0001 1100 upon hardware reset

only.

Memory Select Register

This register contains the decoded bits of the

Memory Select 0-4 switch. For further details,

refer to the Memory Address Decoding section of

this document, as well as Figure 4 and Table 1.

I/O Select Register

This register contains the decoded bits of the I/O

Select 0-2 switch. For further details, refer to the

I/O Address Decoding section of this document,

as well as Figure 6 and Table 2.

Node ID Register

The Node ID Register contains the values of the

Node ID switches. The microprocessor may read

from the Node ID Register at any time for

diagnostic purposes. In addition, the COM90C66

may be put into a special mode whereby the

microprocessor may write to the Node ID

ID. To enter this special mode, the Node ID

switches must be set to 00H. Note that when the

Node ID switches are set to 00H, the COM90C66

is put into a Disable Transmitter mode and it will

not attempt to join the network. When the device

is in the Disable Transmitter mode, tokens are

not passed and reconfigurations are not

generated by the node. The Receiver portion of

the device will provide the user with useful

information about the network. The device will

not attempt to rejoin the network until a valid

Node ID value is placed into the Node ID

Disable Transmit mode, when the Node ID

switches are set to 00H, the RAM of the

COM90C66 is kept hidden from the

microprocessor. The RAM may be enabled by

issuing a software reset, followed by a valid write

to the Node ID Register. Refer to the System

Reset Logic section for details on resetting the

device in a non-IBM-compatible environment.

The I/O address of the Node ID Register is 05H.

Tables 3 and 4 illustrate the Node ID Register, as

well as the other registers of the COM90C66.

The Node ID Register defaults to the value 0000

0000 upon hardware reset only.

External Register

The optional write only external register may be

used for application-dependent functions. A read

operation at this location will provide invalid data.

Whenever a write to address 07H occurs, the

COM90C66 activates the nPROM signal. In this

case, the nPROM signal is to be used as the

nChip Select signal and the nIOW signal should

be used to write to the external register. The

external PROM should use the nPROM signal as

nChip Select and the nMEMR signal as nOutput

Enable, as usual.

Reset Register

Any read or write access to I/O offsets 08H, 09H,

0AH, or OBH generates a software reset. These

four I/O locations were preserved for software

compatibility with the COM90C65 ARCNET

Controller. Refer to the Reset Logic section of

this document for further details.

Data Low and High Registers

These read/write registers are each 8-bits wide

and are used in I/O Mapped Mode only. The

Data Register contains the byte or word which is

meant to be read from or written to the

address location presently specified by the

address pointer. The contents of the Data

Registers are undefined upon hardware reset.

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