COM90C66 Datasheet, PDF (19/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

ADDRESS DECODING
The COM90C66 includes address decoding
circuitry that compares the value of the Address
Bus to the address range selected by the
Memory Select (MS0-MS4) and I/O Select
(IOS0-IOS2) pins in order to determine
processor accesses to the on-board PROM, the
on-chip RAM, and I/O locations. By placing
switches on the MS0-MS4 and the IOS0-IOS2
pins, the user configures the Memory Map and
I/O Map according to the possible address
ranges shown in Tables 1 and 2.
Table 2 - User Configuration of I/O Map
IOS2 I0S1 IOS0 I/O ADDRESS RANGE
0
0
0
0260-026F
0
0
1
0290-029F
0
1
0
02E0-02EF
0
1
1
02F0-02FF
1
0
0
0300-030F
1
0
1
0350-035F
1
1
0
0380-038F
1
1
1
03E0-03EF
Memory Address Decoding
The Memory Address Decoding circuitry is used
to select a block from the memory map of the
processor for PROM and RAM accesses. Figure
4 illustrates how the memory selection works.
The MS4-MS0 pins are decoded through a 5 to
9 Decoder to generate a 9-bit value. These nine
bits are compared to the A19-A11 lines of the
Address Bus in order to select a particular 16K
memory segment. Figure 7 illustrates a 16K
block of memory that has been selected by the
MS4-MS0 pins. The PROM occupies the upper
8K area of the selected 16K segment and is
accessed when A13 = 1. The RAM occupies
one of four selectable 2K areas of the selected
16K segment and is accessed when A13 = 0.
A11 and A12 are used to determine which 2K
segment of the lower 8K area will be used for
the RAM buffer.
Figure 5 illustrates how the external PROM
selection works. The MS4-MS0 pins are
decoded through a 5 to 7 Decoder to generate a
7-bit value. These seven bits are compared to
the A19-A13 lines of the Address Bus in order to
select an 8K memory range. Figure 7 illustrates
an 8K block of memory for the PROM. In I/O
16K x 8 Mode only a 16K memory range is
selected for the PROM. Figure 8 illustrates a
16K block of memory for the PROM.
The nENROM pin is used to enable decoding for
the on-board PROM. If nENROM is connected
to a logic "1", the COM90C66 will not generate
the nPROM signal, the nTOPL signal, or the
IOCHRDY signal for accesses to the PROM. In
this configuration, the COM90C66 will only
occupy a 2K segment of memory.
I/O Address Decoding
This section is used to select a block of 16 I/O
locations from the I/O map of the processor.
Figure 6 illustrates how the I/O selection
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