COM90C66 Datasheet, PDF (42/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

address to be accessed through the Data
Register. If a 1K x 16 space is desired, the A0
bit should be forced to a logic "0" and A1-A10
will be used to load the Address Pointer
Register. A single byte access at the defined
Memory cycles and the Auto Increment Mode.
Refer to Table 14 for signal level requirements
in 16-Bit I/O Mapped Mode.
16-Bit Memory Mapped Mode:
word address is still possible by accessing
either the upper or lower portion of the Data
Register. When the device is configured for
Auto Increment Mode, the access to the upper
portion of the Data Register automatically
In 16-Bit Memory Mapped Mode, the A10-A1
lines of the Address Bus determine the word
address to be accessed, while A0 and nSBHE
determine which byte within the word location
increments the pointer. Refer to the Memory
Vs. I/O Cycles section of this document for
further information on Sequential I/O Mapped
will be accessed. Refer to Table 14 for signal
level requirements in 16-Bit Memory Mapped
accesses.
Table 14 - 8-Bit vs. 16-Bit Signal Level Requirements*
ACCESS
DATA
A0 nSBHE nIOCS16 nMEMCS16 TRANSFER
8-Bit I/O
Address Pointer Low 0
X
1
Accesses
Register
X
D0-D7
Address Pointer High 1
X
1
Register
X
D0-D7
Data Register
X
X
1
X
D0-D7**
Other Registers
X
X
1
X
D0-D7
8-Bit Memory RAM Access
X
X
X
1
D0-D7
16-Bit I/O
Pointer Register
0
0
0
Accesses
Word
X
D0-D7,
D8-D15
Address Pointer Low 0
1
0
Register
X
D0-D7
Address Pointer High 1
0
0
Register
X
D8-D15
Data Register Word 0
0
0
X
D0-D7,
D8-D15**
Even RAM Byte
0
1
0
X
D0-D7
Odd RAM Byte
1
0
0
X
D8-D15**
Other Registers
X
X
1
X
D0-D7
16-Bit Memory RAM Access, Word 0
0
X
Accesses
0
D0-D7,
D8-D15
Even RAM Byte
0
1
X
0
D0-D7
Odd RAM Byte
1
0
X
0
D8-D15
* Any combinations other than those defined above are illegal.
**This access will increment the pointer
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