COM90C66 Datasheet, PDF(38/76 Page) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

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COM90C66 Datasheet, PDF (38/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

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Table 11 - 16-Bit Memory Mapped Decode

ENROM

DECODE

MODE

RAM

MEMCS16

ROM

128K

The internal latches of the COM90C66 go

transparent on BALE high and latch on BALE

low. If all addresses being used are already

latched or valid for the entire duration of the

cycle, then the BALE signal may be tied to a

logic "1".

I/O Mapped Mode:

The system can also be configured as I/O

mapped. In this case, the data transfers to and

from the packet buffer are done by accessing an

I/O location and having the internal pointer in

the device sequentially address memory. The

nIOCS16 signal is activated upon accesses to

the 16-bit pointer register or to the 16-bit data

In the I/O mapped mode, addresses up to A15

are decoded to determine accesses to the

device. On the AT bus the A0-A15 lines are

provided as latched addresses. Therefore, the

BALE signal may be tied to a logic "1". In the

I/O Mode, no memory is used by the board

except for the optional PROM. The nMEMCS16

signal is not used at all.

A logic "0" on the nENROM pin enables ROM

mapping, and in the I/O mapped mode the user

can choose between an 8K or 16K block of

RAM.

Refer to Table 12 for the 16-bit I/O mapped

decode table as a function of the nENROM pin

and the DECODE MODE bit. Refer to Figure

12A for an illustration of the generation of the

nIOCS16 signal.

Table 12 - 16-Bit I/O Mapped Decode

ENROM

DECODE

MODE

RAM

MEMCS16

ROM

I/O

16K

I/O

Wait State Details

In the typical computer, the Bus Speed will be

slower than the CPU speed so that the

peripherals will be able to keep up with the

machine. In many cases, the peripheral will

need additional delays to be able to keep up,

and will therefore use the IOCHRDY signal to

tell the processor whether or not it is ready to

continue. The use of the IOCHRDY signal

effectively "slows down" the bus.

The COM90C66 is quick enough to take

advantage of the maximum bus speed of most

AT compatibles. The function employs the use

of the nOWS signal and guarantees the fastest

microprocessor cycles. The use of the nOWS

signal effectively "speeds up" the bus.

Upon power up, the COM90C66 defaults to the

non-zero wait state mode. The nOWS mode

can be easily configured by writing a logic "0"

into bit 2 of the Configuration Register.

For machines with faster buses, the COM90C66

can be configured to negate the IOCHRDY line

for the minimal period of time necessary. If the

IOCHRDY signal is used, it is negated for one

XTAL1 clock for RAM and internal register

cycles. If the optional PROM is on board, it

might require a slower cycle to accommodate its

access time even if the device is configured for

Zero Wait State Mode. When the nENROM

signal is active (logic "0"), the COM90C66 will

negate the IOCHRDY signal for two XTAL1

clocks on ROM read accesses. If the optional

external register is used, I/O Write

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