COM90C66 Datasheet, PDF (49/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

TIMING DIAGRAMS
The AC parameters in Figures 14-26 are preliminary. Enhancements will follow.
nMEMR,
nMEMW,
nIOR, or
nIOW
t1
t2
t3
nOWS**
IOCHRDY**
t4
t5
Parameter
t1
Control Signal Pulse Width
t2
Control Signal Low to nOWS Low
t3
Control Signal High to nOWS High
t4
Control Signal Low to IOCHRDY Low
t5
IOCHRDY Low Pulse Width
min
typ max units
80
*
nS
0
20
nS
0
20 nS
0
20
nS
50
115 nS
* 1.2 uS for back-to-back 8-bit cycles
2.5 uS for 16-bit cycles
** These signals are mutually exclusive. Only one signal is active on any given board, depending
on the WAIT STATE bit of the Configuration Register.
FIGURE 14 - ZERO WAIT STATE AND IOCHRDY TIMING
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