COM90C66 Datasheet, PDF (52/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

AEN
A0-A15,
nSBHE
BALE
nIOR
D0-D7 or
D0-D15
nTOPH,
nTOPL
nIOCS16
VALID
t1
t2
t3
t6
t4
t5
t10
t9
**
t8
VALID DATA
t7
Parameter
min
typ max units
t1 Address, nSBHE Set Up to BALE Low *
20
nS
t2 Address, nSBHE Hold after BALE Low *
20
nS
t3 Address, nSBHE, AEN Set Up to nIOR Low
25
nS
t4 nIOR Low to Valid Data
t5 ^{nIOR Low to nTOPH, nTOPL Low}
0
t6 ^{A2-A15 Valid, AEN Low, BALE High to nIOCS16 Low 0}
t7 ^{nIOR High to nTOPH, nTOPL High}
0
t8 ^{nIOR High to Data High Impedance}
0
80 nS
30 nS
25 nS
15 nS
20 nS
t9 nIOR High to BALE High (Next Address)
30
nS
t10 AEN Hold after nIOR High
10
nS
* For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address
Mode.
** 130 nS minimum inactive time on consecutive reads from Data Register of the COM90C66.
FIGURE 17 - READ I/O CYCLE
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