COM90C66 Datasheet, PDF (71/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

A0-A19
nSBHE
BALE
nMEMR
D0-D7or
D0-D15
nTOPH,
nTOPL
nMEMCS16
(Unlatched)
nMEMCS16
(Latched)
Modified Version of Page 50 for Rev. D COM90C66 Only.
VALID
t2
t1
t2***
t3
t4
t6
t5
t7
t10
VALID DATA
**
t9
t8
t11
Parameter
t1 Address, nSBHE Set Up to BALE Low *
t2 Address, nSBHE Hold after BALE Low *
t3 Address, nSBHE Set Up to nMEMR Low
t4 nMEMR Low to Valid Data
t5 nMEMR Low to nTOPH, nTOPL Low
t6 A19-A17 to nMEMCS16 Low (Unlatched) (128K RAM Decode)
t7 A19-A11 to nMEMCS16 Low (Latched) (2K RAM Decode)
t8 nMEMR High to nTOPH, nTOPL High
t9 nMEMR High to Data High Impedance
t10 nMEMR High to BALE High (Next Address)
t11 Address, nSBHE invalid to nMEMCS16 High
min typ max units
20
nS
20
nS
25
nS
80 nS
0
30 nS
0
40 nS
0
25 nS
0
15 nS
0
20 nS
30
nS
0
nS
* For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address
Mode
** 130ns minimum inactive time on consective memory reads from the COM90C66.
*** ^{For Revision D devices, if BALE is tied high, then Address, nSBHE must be held for 20nsec}
after nMEMR Low.
FIGURE 15 - READ RAM CYCLE
71