COM90C66 Datasheet, PDF (27/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

BIT
BIT NAME
2 Wait State
1 I/O Access
0 Transmitter Off
Table 8 - Configuration Register
SYMBOL
DESCRIPTION
WAIT
This bit is used to select the type of cycle. A logic "1" on this
bit negates the IOCHRDY signal for approximately one or two
XTAL1 clocks, creating one wait state. A logic "0" selects
zero wait state arbitration to the buffer RAM and generates
the Zero Wait State signal. Refer to the wait State Details
section of this document for further information. This bit
defaults to a logic "1" upon hardware reset.
IO-
ACCESS
A logic "1" on this bit configures the buffer RAM for sequential
I/O mapped accesses, while a logic "0" configures the buffer
RAM for memory mapped accesses. This bit defaults to a
logic "0" upon hardware reset.
TXOFF
A logic "1" on this bit disables the transmitter of the
COM90C66, while the receiver remains functional. A logic "0"
keeps the transmitter enabled. This bit may be used in
diagnostic troubleshooting of the network or node. Refer to
the Improved Diagnostics section of this document for further
details. This bit defaults to a logic "0" upon hardware reset.
BIT
BIT NAME
7-0 Address 7-0
BIT
BIT NAME
7, (not used)
5-3
6 Auto Increment
2-0 Address 10-8
Table 9 - Address Pointer Low Register
SYMBOL
DESCRIPTION
A7-A0
These bits hold the lower eight address bits which provide the
addresses to the on-chip RAM.
Table 10 - Address Pointer High Register
SYMBOL
DESCRIPTION
These bits are undefined.
AUTO-
INC
A10-A8
This bit controls whether or not the address pointer will
increment automatically when the device is in I/O Mapping
Mode. A logic "1" on this bit will automatically increment the
pointer after each access. A logic "0" will disable this
function. Please refer to the Memory Vs. I/O section of this
document for further detail.
These bits hold the upper three address bits which provide
the addresses to the on-chip RAM.
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