COM90C66 Datasheet, PDF (35/76 Pages) SMSC Corporation – ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

used by the internal digital filter, which filters
short glitches to only allow valid resets to occur.
A software reset is generated when the
microprocessor accesses I/O locations 8, 9, A, or
B.
Upon reset, the transmitter portion of the device
is disabled and the internal registers assume
those states outlined in the Internal Registers
section.
The COM90C66 will start 102.4 µS after the
RESET IN signal is removed. Please note that
the internal RAM buffer cannot be seen by the
processor unless a software reset is issued.
Therefore, following power up or hardware reset,
a software reset must be issued. Please refer to
System Reset Logic for the steps to bring the
device out of reset. As the device comes out of
reset, the COM90C66, after reading its own ID,
will execute two write cycles to the RAM buffer.
Address 00 HEX will be written with the data D1
HEX and the address 01 HEX will be written with
the ID number read from the Node ID Select
Switch. The processor may then read RAM
buffer address 01 to determine the COM90C66
ID. It should be noted that the data pattern D1
written into the RAM has been chosen arbitrarily.
Only if the D1 pattern appears in the RAM buffer
can proper operation be assured.
System Reset Logic
The IBM AT Bus automatically provides
continuously running cycles for nMEMR,
nMEMW, nIOR, and nIOWn which are utilized by
the COM90C66 in its internal reset sequence.
Buses other than the IBM AT (or compatible)
typically do not provide continuously running
cycles. In this case, the user will need to note
the following COM90C66 internal reset sequence
so that the software interface will provide the
proper accesses utilized by the device. Please
refer to Figure 10.
By satisfying
the simple requirements below, the user can be
assured proper operation of the COM90C66's
reset sequence in a non-IBM AT environment.
A hardware or software reset begins the
COM90C66's internal Power On Reset. Certain
steps must be taken to bring the device out of
reset. In the case of a hardware reset with the
Node ID Switches set to 00H in a non-AT or XT-
compatible, the following steps should be taken:
1. Hardware Reset
2. Dummy access cycle (nMEMR, nMEMW,
nIOR or nIOW) to end the internal Power On
Reset
3. Write to the Node ID Register
4. Wait 114.4 µs (or 256 bit clocks + 12 µs)
5. Dummy access cycle
6. Write to the Configuration Register
7. Software Reset to wake up the internal RAM
8. Dummy access cycle
9. Write to the Node ID Register
10. Wait 114.4 µs (or 256 bit clocks + 12 µs)
11. Dummy access cycle
If only a software reset occurred, then steps 1-7
are not necessary. If the Node ID Switches are
set to a value other than 00, then steps 3 and 9
are not necessary. If the machine is an AT- or
XT-compatible, then steps 2, 5, 8 and 11 are not
necessary. Once these steps are taken, the
COM90C66 comes out of reset. Any accesses
thereafter are considered valid accesses.
READ AND WRITE CYCLES
Memory vs. I/O Cycles
In addition to Memory Mapping, the COM90C66
performs Sequential I/O Mapped Memory
accesses, thus a packet that is placed in the
internal RAM buffer can be accessed by
addressing only one 8- or 16-bit I/O location. The
processor places the address that needs to be
accessed into the Address Pointer by writing
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