C8051F388 Datasheet, PDF (96/285 Pages) –

C8051F388/9/A/B
14.6. Timing
The timing parameters of the External Memory Interface can be configured to enable connection to
devices having different setup and hold time requirements. The Address Setup time, Address Hold time,
RD and WR strobe widths, and in multiplexed mode, the width of the ALE pulse are all programmable in
units of SYSCLK periods through EMI0TC, shown in SFR Definition 14.3, and EMI0CF[1:0].
The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing
parameters defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution
time for an off-chip XRAM operation is 5 SYSCLK cycles (1 SYSCLK for RD or WR pulse + 4 SYSCLKs).
For multiplexed operations, the Address Latch Enable signal will require a minimum of 2 additional
SYSCLK cycles. Therefore, the minimum execution time for an off-chip XRAM operation in multiplexed
mode is 7 SYSCLK cycles (2 for ALE + 1 for RD or WR + 4). The programmable setup and hold times
default to the maximum delay settings after a reset. Table 14.1 lists the AC parameters for the External
Memory Interface, and Figure 14.4 through Figure 14.9 show the timing diagrams for the different External
Memory Interface modes and MOVX operations.
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