C8051F388 Datasheet, PDF (140/285 Pages) –

C8051F388/9/A/B
SFR Definition 19.3. OSCICN: Internal H-F Oscillator Control
Bit
7
6
5
4
3
2
1
0
Name IOSCEN IFRDY SUSPEND
IFCN[1:0]
Type R/W
R
R/W
R
R
R
R/W
Reset
1
1
0
0
0
0
0
0
SFR Address = 0xB2; SFR Page = All Pages
Bit Name
Function
7 IOSCEN Internal H-F Oscillator Enable Bit.
0: Internal H-F Oscillator Disabled.
1: Internal H-F Oscillator Enabled.
6
IFRDY Internal H-F Oscillator Frequency Ready Flag.
0: Internal H-F Oscillator is not running at programmed frequency.
1: Internal H-F Oscillator is running at programmed frequency.
5 SUSPEND Internal Oscillator Suspend Enable Bit.
Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The inter-
nal oscillator resumes operation when one of the SUSPEND mode awakening
events occurs.
4:2 Unused Read = 000b; Write = don’t care
1:0 IFCN[1:0] Internal H-F Oscillator Frequency Divider Control Bits.
The Internal H-F Oscillator is divided by the IFCN bit setting after a divide-by-4 stage.
00: SYSCLK can be derived from Internal H-F Oscillator divided by 8 (1.5 MHz).
01: SYSCLK can be derived from Internal H-F Oscillator divided by 4 (3 MHz).
10: SYSCLK can be derived from Internal H-F Oscillator divided by 2 (6 MHz).
11: SYSCLK can be derived from Internal H-F Oscillator divided by 1 (12 MHz).
140
Rev. 1.1