C8051F388 Datasheet, PDF (73/285 Pages) –

C8051F388/9/A/B
Reset” on page 127 for more information on the use and configuration of the WDT.
10.2. Stop Mode
Setting the stop mode Select bit (PCON.1) causes the controller core to enter stop mode as soon as the
instruction that sets the bit completes execution. In stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering stop mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout.
By default, when in stop mode the internal regulator is still active. However, the regulator can be config-
ured to shut down while in stop mode to save power. To shut down the regulator in stop mode, the
STOPCF bit in register REG01CN should be set to 1 prior to setting the STOP bit (see SFR Definition 9.1).
If the regulator is shut down using the STOPCF bit, only the RST pin or a full power cycle are capable of
resetting the device.
10.3. Suspend Mode
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the high-frequency internal oscillator
and go into suspend mode as soon as the instruction that sets the bit completes execution. All internal reg-
isters and memory maintain their original data. The CPU is not halted in Suspend, so code can still be exe-
cuted using an oscillator other than the internal high-frequency oscillator.
Suspend mode can be terminated by a rising or falling edge on the INT2 pin or a device reset event. When
suspend mode is terminated, if the oscillator source is the internal high-frequency oscillator, the device will
continue execution on the instruction following the one that set the SUSPEND bit. If the wake event was
configured to generate an interrupt, the interrupt will be serviced upon waking the device. If suspend mode
is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins
program execution at address 0x0000.
Rev. 1.1
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