C8051F388 Datasheet, PDF (254/285 Pages) –

C8051F388/9/A/B
25.5. Timer 5
Timer 5 is a 16-bit timer formed by two 8-bit SFRs: TMR5L (low byte) and TMR5H (high byte). Timer 5 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T5SPLIT bit (TMR5CN.3) defines
Timer 5 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. Note that the external oscillator source divided by 8 is synchronized with the system
clock.
25.5.1. 16-bit Timer with Auto-Reload
When T5SPLIT (TMR5CN.3) is zero, Timer 5 operates as a 16-bit timer with auto-reload. Timer 5 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 5
reload registers (TMR5RLH and TMR5RLL) is loaded into the Timer 5 register as shown in Figure 25.14,
and the Timer 5 High Byte Overflow Flag (TMR5CN.7) is set. If Timer 5 interrupts are enabled (if EIE1.7 is
set), an interrupt will be generated on each Timer 5 overflow. Additionally, if Timer 5 interrupts are enabled
and the TF5LEN bit is set (TMR5CN.5), an interrupt will be generated each time the lower 8 bits (TMR5L)
overflow from 0xFF to 0x00.
Figure 25.14. Timer 5 16-Bit Mode Block Diagram
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Rev. 1.1