C8051F388 Datasheet, PDF (49/285 Pages) –

C8051F388/9/A/B
SFR Definition 6.1. ADC0CF: ADC0 Configuration
Bit
7
Name
Type
Reset
1
6
5
4
AD0SC[4:0]
R/W
1
1
1
3
2
1
0
AD0LJST
Reserved
R/W
R/W
1
0
0
0
SFR Address = 0xBC; SFR Page = All Pages
Bit Name
Function
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock
requirements are given in the ADC specification table.
AD0SC = -S----Y----S----C----L---K--- – 1
CLKSAR
Note: If the Memory Power Controller is enabled (MPCE = '1'), AD0SC must be set to at least
"00001" for proper ADC operation.
2 AD0LJST ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Note: The AD0LJST bit is only valid for 10-bit mode (AD08BE = 0).
1:0 Reserved Must Write 00b.
Rev. 1.1
49