C8051F388 Datasheet, PDF (246/285 Pages) –

C8051F388/9/A/B
SFR Definition 25.14. TMR3CN: Timer 3 Control
Bit
7
6
5
4
3
2
1
0
Name TF3H
TF3L TF3LEN TF3CEN T3SPLIT TR3
T3CSS T3XCLK
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x91; SFR Page = 0
Bit
Name
Function
7
TF3H Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the
Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3
interrupt service routine. This bit is not automatically cleared by hardware.
6
TF3L Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will
be set when the low byte overflows regardless of the Timer 3 mode. This bit is not
automatically cleared by hardware.
5 TF3LEN Timer 3 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
4 TF3CEN Timer 3 Low-Frequency Oscillator Capture Enable.
When set to 1, this bit enables Timer 3 Low-Frequency Oscillator Capture Mode. If
TF3CEN is set and Timer 3 interrupts are enabled, an interrupt will be generated on
a falling edge of the low-frequency oscillator output, and the current 16-bit timer
value in TMR3H:TMR3L will be copied to TMR3RLH:TMR3RLL.
3 T3SPLIT Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
2
TR3
Timer 3 Run Control.
Timer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR3H only; TMR3L is always enabled in split mode.
1
T3CSS Timer 3 Capture Source Select.
This bit selects the source of a capture event when bit T2CE is set to 1.
0: Reserved.
1: Capture source is falling edge of Low-Frequency Oscillator.
0 T3XCLK Timer 3 External Clock Select.
This bit selects the external clock source for Timer 3. However, the Timer 3 Clock
Select bits (T3MH and T3ML in register CKCON) may still be used to select between
the external clock and the system clock for either timer.
0: Timer 3 clock is the system clock divided by 12.
1: Timer 3 clock is the external clock divided by 8 (synchronized with SYSCLK).
246
Rev. 1.1