C8051F388 Datasheet, PDF (182/285 Pages) –

C8051F388/9/A/B
21.4.5. Data Register
The SMBus Data register SMBnDAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SIn flag is set. Software should
not attempt to access the SMBnDAT register when the SMBus is enabled and the SIn flag is cleared to
logic 0, as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMBnDAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMBnDAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMBnDAT always contains the last data byte present on the bus. In the event of lost arbi-
tration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMBnDAT.
SFR Definition 21.10. SMB0DAT: SMBus Data
Bit
7
6
5
4
3
2
1
0
Name
SMB0DAT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC2; SFR Page = 0
Bit
Name
Function
7:0 SMB0DAT[7:0] SMBus0 Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus0
serial interface or a byte that has just been received on the SMBus0 serial inter-
face. The CPU can read from or write to this register whenever the SI0 serial inter-
rupt flag (SMB0CN.0) is set to logic 1. The serial data in the register remains stable
as long as the SI0 flag is set. When the SI0 flag is not set, the system may be in the
process of shifting data in/out and the CPU should not attempt to access this regis-
ter.
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Rev. 1.1